Non-volatile data storage devices, such as embedded memory devices (e.g., embedded MultiMedia Card (eMMC) devices) and removable memory devices (e.g., removable universal serial bus (USB) flash memory devices and other removable storage cards), have allowed for increased portability of data and software applications. Users of non-volatile data storage devices increasingly rely on the non-volatile storage devices to store and provide rapid access to a large amount of data.
Many different decoding techniques (e.g., decoding schemes) are available to decode encoded data used in digital communication and storage systems, such as in non-volatile data storage devices. For example, low-density parity-check (LDPC) codes are error correcting codes (e.g., decoding codes) used in numerous systems. Layered decoding is a technique that can be adopted to reduce the complexity of LDPC decoders. In traditional layered decoders for Quasi-cyclic (QC) LDPC codes, each layer consists of one block row of a parity check matrix associated with the LDPC code. Although a proposed multi-block-row layered decoder has a reduced number of clock cycles, a clock frequency (e.g., a clock period) of the proposed multi-block-row layered decoder is limited due to a long “critical path” (e.g., a longest combinational logical path). Thus, there is a need for an improved multi-block-row layered decoder.